In general, an image sensor is a semiconductor device for converting an optical image into an electrical signal. The image sensor is roughly classified as a charge coupled device (CCD) or a CMOS image sensor (CIS).
The CCD includes a plurality of photodiodes (PDs) arranged in a matrix to convert light signal into an electrical signal. The CCD also includes a plurality of vertical charge coupled devices (VCCDs), a plurality of horizontal charged coupled devices (HCCDs), and a sense amplifier. The VCCDs are formed between the PDs vertically arranged in a matrix to transmit charge created from each of the PDs in a vertical direction. The HCCDs transmit the charge transmitted through each VCCD in a horizontal direction, and the sense amplifier senses the charge transmitted in the horizontal direction to output an electrical signal.
However, the CCD not only has a complicated driving method and high power consumption but also requires a plurality of photolithography processes.
Also, in the CCD, it is difficult to integrate a control circuit, a signal processing circuit, and an analog/digital converter (A/D converter) into a single CCD chip, so that the product is hard to miniaturize.
Recently, a CMOS image sensor (CIS) is in the limelight as a next generation image sensor for overcoming disadvantages of the CCD.
The CIS is a device that sequentially detects an output of each unit pixel using MOS transistors by forming the MOS transistors in each of the unit pixels on a semiconductor substrate using a CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits.
That is, the CIS provides photodiodes and MOS transistors within a unit pixel to sequentially detect an electrical signal of each unit pixel in a switching manner, and realize an image.
Since the CIS is manufactured using the CMOS technology, it has the advantages of relatively low power consumption and a simple manufacturing process using a relatively small number of photolithography processes.
Also, it is possible to integrate a control circuit, a signal processing circuit, and an A/D converter into a single CIS chip, so that a product can be easily miniaturized.
Therefore, CISs are widely used for various applications such as digital still cameras and digital video cameras.
CISs are classified as 3T type CMOS image sensors, 4T type CMOS image sensors, or 5T type CMOS image sensors depending on the number of transistors formed in each unit pixel. The 3T type CMOS image sensor includes one photodiode PD and three transistors. The 4T type CMOS image sensor includes one PD and four transistors.
A conventional 4T type CIS will be described below.
FIG. 1 is an equivalent circuit diagram of a general 4T type CIS, and FIG. 2 is a lay-out diagram illustrating a unit pixel of a general 4T type CIS.
Referring to FIG. 1, a unit pixel 100 of the 4T type CIS includes a PD 10 as a photo-electric converting part, and four transistors.
The four transistors 20, 30, 40, and 50 are transfer, reset, drive, and select transistors, respectively. In addition, a load transistor 60 is electrically connected to an output end of the pixel 100.
In FIG. 1, FD is a floating diffusion, Tx is the gate voltage of the transfer transistor 20, Rx is the gate voltage of the reset transistor 30, Dx is the gate voltage of the drive transistor 40, and Sx is the gate voltage of the select transistor 50.
Referring to FIG. 2, an active region is defined in a unit pixel of the general 4T type CIS. A device isolation layer is formed on a portion of the substrate to define the active region. A PD is formed in a portion of the active region that has a wide width, and gate electrodes 23, 33, 43, and 53 of four transistors are formed overlapping the remaining portion of the active region.
That is, the transfer, reset, drive, and select transistors 20, 30, 40, and 50 are formed by the gate electrode 23, 33, 43, and 53, respectively.
Here, source/drain regions of the transistors 20, 30, 40, and 50 are formed by implanting impurity ions into portions of the active region around the gate electrodes 23, 33, 43, and 53.
FIG. 3 is a plan view illustrating a Bayer pattern of general color filters.
Referring to FIG. 3, color filters are arranged in an order of green (G), blue (B), C, and B on a first row. Also, color filters are arranged in an order of red (R), G, R, and G on a second row to correspond to the first row.
That is, Cs are arranged in a W-shape, Bs are arranged inside a V-shape of the W-shape, and Rs are arranged outside the V-shape of the W-shape.
FIGS. 4A to 4G are cross-sectional views, taken along a line I-I′ of FIG. 2, explaining a method for manufacturing a CIS according to a related art.
Referring to FIG. 4A, an epitaxial process is performed on a high concentration P++-type semiconductor substrate 61 to form a low concentration P-type epitaxial layer 62.
Subsequently, an active region and a device isolation region are defined in the semiconductor substrate 61. A device isolation layer 63 is formed in the device isolation region using a shallow trench isolation (STI) process or a local oxidation of silicon (LOCOS) process.
Also, a gate insulating layer 64 and a conductive layer (e.g., a high concentration polysilicon layer) are sequentially deposited on an entire surface of the epitaxial layer 62 in which the device isolation layer 63 has been formed. The conductive layer and the gate insulating layer are selectively removed to form a gate electrode 65.
Referring to FIG. 4B, a first photoresist layer 65 is coated on an entire surface of the semiconductor substrate 61, and patterned to expose respective PD regions of Bs, Gs, and Rs using exposure and development processes.
Also, blue, green, and red PD regions 67 are formed by implanting low concentration n−-type impurity ions into the epitaxial layer 62 using the patterned first photoresist layer 66 as a mask.
Each PD region 67 serves as a source region of the reset transistor (Rx of FIGS. 1 and 2).
When a reverse bias is applied between each PD region 67 and the low concentration P-type epitaxial layer 62, a depletion layer is created. Electrons created by receiving light from the PD region reduce a potential of the drive transistor when the reset transistor is turned off. The electrons reduce the potential constantly from a point when the reset transistor is turned off after being turned on, so that a voltage difference is generated. This voltage difference is used for processing a signal and thus operates an image sensor.
Here, the PD regions 67 are formed to have the same depth of about 2-3 μm.
That is, the PD regions 67 are formed to each have the same depth by implanting impurity ions using the same ion implantation energy.
Referring to FIG. 4C, a sidewall insulating layer 68 is formed on side portions of the gate electrode 65 by completely removing the first photoresist layer 66, depositing an insulating layer on an entire surface of the semiconductor substrate 61, and performing an etch-back process on the insulating layer.
Subsequently, a second photoresist layer 69 is coated on an entire surface of the semiconductor substrate 61, and patterned to cover the PD region and expose source/drain regions of the transistors using exposure and development processes.
Also, an n+-type diffusion region 70 is formed by implanting high concentration n+-type impurity ions in the exposed source/drain regions using the patterned second photoresist layer 69 as a mask.
Referring to FIG. 4D, the second photoresist layer 69 is removed, a third photoresist layer 71 is coated on an entire surface of the semiconductor substrate 61 and patterned to expose respective PD regions using exposure and development processes.
Subsequently, a p0-type diffusion region 72 is formed within a surface of the semiconductor substrate by implanting p0-type impurity ions into the PD region 67 in which the n−-type diffusion region has been formed using the patterned third photoresist layer 71 as a mask.
Here, the p0-type diffusion region 72 is formed to a depth of 0.1 μm or less.
Referring to FIG. 4E, the third photoresist layer 71 is removed, and a heat treatment process is performed on the semiconductor substrate 61 to diffuse respective impurity diffusion regions.
Subsequently, an interlayer insulating layer 73 is formed on an entire surface of the semiconductor substrate 61. A variety of metal lines (not shown) are formed by depositing a metal layer on the interlayer insulating layer 73 and selectively patterning the metal layer.
The interlayer insulating layer 73 and the metal lines can be formed in a plurality of layers.
A first overcoat layer 74 is formed on the interlayer insulating layer 73.
Referring to FIG. 4F, a color filter layer 75 including color filters is formed by coating blue, red, and green resist layers on the first overcoat layer 74, and performing exposure and development processes on the resist layers. The color filters of the color filter layer filter light for respective wavelength bands.
At this point, since the respective color filters are formed by different photolithography processes, they have different height differences, respectively.
Referring to FIG. 4G, a second overcoat layer 76 is formed on an entire surface of the semiconductor substrate 61 including the color filter layer 75 on which a planarization has been performed. After that, a material layer for forming a microlens is coated on the second overcoat layer 76, and patterned to form microlens patterns using exposure and development processes.
Subsequently, microlenses 77 are formed by performing a reflow process on the microlens patterns.
However, the above-described method for manufacturing a CIS according to the related art has the following problems.
That is, since PDs of blue, green, and red colors, which are primary colors, are formed to have the same depth. The primary colors have serious differences in penetrating depth from a surface of a silicon substrate to PDs corresponding to R, B, and G because of a difference in their wavelength in association with a lattice structure of silicon. Particularly, the PDs do not function effectively with respect to blue and red pixels, which reduces characteristics of the image sensor.